Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Due to the growing demand for higher densities, a continuous increase in array density and the scaling of the supply voltage become mandatory. There have been may attempts to solve this problem by the fabrication of high-performance flash memory devices using polysilicon spacer technology. For example, in “sidewall gate” device applications, a floating gate is formed of a first polysilicon layer, while a select gate is formed of a polysilicon spacer. Also, a so-called Halo SONOS device, in the paper “Embedded Twin MONOS Flash Memories with 4 ns and 15 ns Fast Access Times” by Tomoko et al., presented in 2003 symposium on VLSI technology digest of technical papers, contains a word gate and polysilicon spacers acting dual sidewall control gates. In addition, one unique memory, Direct Tunneling Memory (DTM), in the paper “Ultra-High Speed Direct Tunneling (DTM) for Embedded RAM Application”, presented in 2004 symposium on VLSI technology digest of technical papers, uses sidewall control gates formed of polysilicon on both sides of a floating gate and offset source/drain regions without overlapping the floating gate.
Typically, the polysilicon spacer technology includes depositing a polysilicon layer on the chip and then partially selectively removing the polysilicon layer by using anisotropic dry etch techniques. It is, however, very difficult to control this selective etching operation, for example the spacer uniformity of shape, width, thickness and the like after etching. FIG. 1 is a cross-sectional diagram illustrating a conventional memory device with a pair of polysilicon spacers. In general, an oxide layer and a first polysilicon layer are successively deposited on a semiconductor substrate 10 and then patterned as a gate oxide layer 12 and a polysilicon gate 14 from the use of photolithography and etching process. Next, an integrated dielectric layer 16 is conformally deposited on the substrate 10 and sidewalls of the polysilicon gate 14. Then a second polysilicon layer is deposited followed by an anisotropic etch-back process, which forms polysilicon spacers 18 on opposite sides of the polysilicon gate 14. The integrated dielectric layer 16 is also etched, leaving this integrated dielectric layer 16 only underlying the polysilicon spacers 18. After forming source/drain regions 20 in the substrate 10, a silicidation process is performed to form metal silicide layers 22 on the exposed surfaces of the polysilicon gate 14 and the source/drain regions 20 respectively.
The anisotropic etch-back process, however, cannot well control dimensions and profiles of the polysilicon spacers 18 to facilitate proper device design. Also, this etch-back step often damages the integrated dielectric layer 16 to cause a cave thereon, thus a subsequent silicidation process cannot be perfectly performed. Particularly, due to damages to the integrated dielectric layer 16, undesired metal silicide regions 22a exists on the damaged portion of the integrated dielectric layer 16 during the subsequent silicidation step, resulting in a shortage path bridging the polysilicon gate 14 and the polysilicon spacer 18.
It is therefore desirable to provide a novel profile of the non-volatile memory device for preventing a shortage path between the polysilicon gate and the polysilicon spacer during a silicidation process.